1. Field of the Invention
The present invention relates to a semiconductor chip structure having at least one contact bump, and more particularly to a semiconductor chip structure with a plurality of contact bumps, wherein a given contact bump formed on an electrode pad of the semiconductor substrate is differently sized with respect to an X-axis direction and an Y-axis direction and, at the same time, an elongated offset formed in the upper portion of the bump is formed with its curvature only along a transverse direction, thereby preventing a bonding failure between the bump and lead due to the offset of the bump.
2. Description of Related Art
Generally, semiconductor chips of integrated circuits, large-scale integrated circuits, and the like are sealed in a package type of encapsulating resin, and mounted on a printed circuit board (hereinafter referred to as "PCB").
The semiconductor chip is typically mounted on a square die pad via a die attachment process, with input/output lead pins being arranged on the sides of the die pad by a predetermined interval. One end of the lead is connected by a wire to an electrode pad of the semiconductor chip via a wire bonding process.
Also, a package body is protectively formed via a molding process around the semiconductor chip and wires. Other ends of the leads protrude from one side of the package, and are bent via a bending process to be suitable for mounting.
Along with the trend towards manufacturing lightweight, simplified, and miniaturized semiconductor products, larger pin counts and thinness are continuously sought in semiconductor packages for high density mounting, but improvements in mounting is limited when using the conventional semiconductor package.
Therefore, a chip on board ("COB") method for directly mounting bare chips onto the PCB, a tape automated bonding ("TAB") method (wherein die pads and wires, which occupy a significant area in a semiconductor package, are eliminated) to directly attach bare chips to leads, and similar methods are newly-developed and employed.
According to the TAB method, contact bumps of a predetermined height are formed on the electrode pads of the semiconductor chips, and thin leads are thermally compressed onto the bumps to attach them.
In the TAB package, which is a kind of a surface mounting technique, one end of the lead having a thin copper film subjected to a photo lithography on an insulating film is connected to a bump formed on the electrode pad of the semiconductor chip. The TAB package has been used in a low pin-small chip apparatus such as a watch and a calculator, and is being pursued in large-sized memory devices with multiple pin counts such as a liquid crystal display driver, ASIC and a microcomputer.
The semiconductor chip bumps applied to the semiconductor package are generally formed through an electroplating method having an excellent productivity, a transferring process, or a dotting method of a photoresist-type conductive layer for selectively forming the bumps by identifying defective chips.
FIGS. 1A to 4 illustrate a conventional semiconductor chip bump 16 which will be utilized for description. Here, the same parts are designated by same reference numerals.
FIG. 1A is a plan view schematically showing the upper surface of an electrode pad formed on a semiconductor substrate. FIG. 1B is a section view of the semiconductor structure longitudinally cutting FIG. 1 in an Y-axis direction. FIG. 1C is a cross section view cutting FIG. 1A in an X-axis direction.
Referring to FIG. 1A, a rectangular electrode pad 12 made from an aluminum material like aluminum or an aluminum alloy and connected to a signal line 11 is formed on a semiconductor substrate 10 as part of a predetermined circuit thereon. A passivation layer 14 having a double layer structure obtained by sequentially stacking layers of predetermined materials, (e.g., a silicon oxide layer 13 and a silicon nitride layer 15) is formed on the surface of the surface of the semiconductor substrate 10 having pad 12 formed thereon.
At this time, the central portion of the electrode pad 12 is then exposed through passivation layer 14 through an opening of a predetermined shape, (e.g., an octagon obtained by cutting corners of a regular square or the uncut regular square). The silicon nitride layer 15 of passivation layer 14 covers an edge of the silicon oxide layer 13 adjacent to this opening by approximately 5 .mu.m.
A barrier metal layer (not shown) is formed of a metal having excellent processing and attachment properties is formed over the aluminum electrode pad 12 exposed by the opening in passivation layer 14 and on the upper portion of the edge of the passivation layer 14, to improve the bonding force of the bump 16 and to prevent diffusion to the electrode pad 12.
Referring to FIGS. 1B and 1C for observing the above-described structure, the bump 16 is formed via the electroplating method, and is smaller in dimension than the overall electrode pad 12, but greater in dimension than the portion of the electrode pad 12 exposed by the contact window in the passivation layer 14.
The electroplating method is performed in such a manner that the semiconductor substrate 10 having the barrier metal layer exposed via a photoresist pattern formed thereover (not shown) is immersed into a plating solution of gold (Au). Then, a predetermined voltage is supplied to the barrier metal layer to form the bump 16, and then portions of the barrier metal layer left exposed around the photo resist pattern and around the bump 16 are eliminated.
When viewed from the top, the bump 16 is squared (see FIG. 1A), and the center of the upper surface of the bump 16 is hollowed or dimpled to form an offset A between the center and the periphery, so that the overall shape crater-like or bowl-like.
FIG. 2 is a plan view showing a lead attached on the conventional bump 16 formed on the upper surface of the electrode pad shown in FIG. 1A.
Referring to FIG. 2, lead 18 composed of the thin copper film is attached onto the bump 16 formed as above via a thermal compression method. A tin (Sn) film (not shown) is coated on one side of the lead 18 to improve bonding force between the lead 18 and the bump 16, and a fillet 19, formed of an alloy of gold (Au) and tin (Sn), is formed on the junction portion with the bump 16.
Since the above-described conventional bump is bowl-like with a hollowed center thereof, there is an offset A between the periphery and center portions of the chip bump 16. Thus, as can be noted from the section views shown in FIGS. 3 and 4, the lead 18 connect to the bump 16 contacts the bump 16 only a periphery of the bump 16 surrounding the bowl-like area. Junction resistance is thereby increased, which causes noise and degrades the reliability of the semiconductor package.
Moreover, the bonding force between the lead and bump is so weak (by about 20 to 35 gr) that a rate of contact shorting of the lead reaches about 30%, thereby lowering yield of the semiconductor package.
Therefore, in the above-described methods, the conventional chip bumps are difficult to manufacture in a uniform shape, resulting in problems of manufacturing cost, delivery date, etc. For this reasons, study of ideal processing condition which do not produce the offset of the bump via the common electroplating method, of the designing state of the electrode pad, and the like has been actively conducted.
For example, as disclosed in "Optimization of a Gold Bump Process for TAB by Statistically Designed Experimentation" written by David Tovar in ITAB 91 proceeding, pages 1-15, experiments about the influences on the reliability of the semiconductor chip are carried out according to the dimension of a contact window for exposing an electrode pad, the hardness of a bump, and a passivation rate of the surface of a barrier metal layer, which are varied in accordance with conditions of the thermal processing after forming the bump.
However, a bump of an excellent reliability can be obtained under the optimal state without requiring an additional process in manufacturing the bump by finding out the optimal states for process and design, but the optimal state is difficult to determine. Furthermore, if external factors, such as the kind of semiconductor chip and replacement of apparatuses is changed, the optimal state also changes, thereby restricting the range of application.